A Testing Methodology for VHDL Based High-Level Designs
نویسندگان
چکیده
The test problem increasingly affects system design process, related costs and time to market. Requirements from VLSI/WSI manufacturers are for fast and reliable testability tools, with the possibility of their introduction in early phases of design. In this paper we describe the different abstraction levels at which testability analysis will be applied in the REQUEST Project. The global tool-set architecture supporting this analysis will be introduced and commented. All design phases are included in this design flow, from the Data Flow Graph/Control Flow Graph (CDFG/CFG) representations of behaviors (directly derived from VHDL behavioral specifications), down to gate level. The paper will then present an application scenario for the behavioral level, where most of the innovative features have been introduced, including a new behavioral fault model strictly related to the lower levels of abstraction.
منابع مشابه
Enhancing a VHDL Based Design Methodology with Application Specific Data Abstraction
VHDL has successfully been introduced into the design methodology for VLSI ASICs. This paper describes a high-level data abstraction and supporting tool that enhance this methodology in the telecommunication application domain. A significant performance gain was obtained by introducing the data abstraction outside the VHDL simulator. The enhanced methodology has been used in current ASIC design...
متن کاملCombination of Iddq Testing and High Level Atpg
T est generation for today’s complex digital cir cuits is an extr emely computation intensive task. The search space of ATPG can be reduced by starting from higher level circuit descriptions. The integration of alternate testing methodology IDDQ testing is suggested for increasing the efficiency of a high level VHDL based test generator.
متن کاملAnalysis of different protocol descriptions styles in VHDL to High-Level Synthesis
A methodology based on VHDL to obtain protocol descriptions suitable to be synthesized using AMICAL, a VHDL based behavioral synthesis tool, is presented. In order to efficiently obtain synthesized architectures, a number of constraints must be imposed on the writing style of VHDL. An example based on the specification of a high speed protocol is discussed. 1-INTRODUCTION The emergence of new t...
متن کاملSpecification of Control Flow Properties for Verification of Synthesized VHDL Designs
Behavioral speciications in VHDL contain multiple communicating processes. Register level designs synthesized from these speciications contain a data path represented as a netlist and a controller consisting of multiple communicating synchronous nite state machines. These nite state machines together implement the control ow speciied in and implied by the behavioral speciication in VHDL. This p...
متن کاملA Two-Level Approach to Automated Conformance Testing of VHDL Designs
For manufacturers of consumer electronics, conformance testing of embedded software is a vital issue. To improve performance, parts of this software are implemented in hardware, often designed in the Hardware Description Language VHDL. Conformance testing is a time consuming and error-prone process. Thus automating (parts of) this process is essential. There are many tools for test generation a...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2008